The present invention relates to a semiconductor design technology, and more particularly, to an internal voltage generating circuit for generating a stable internal voltage.
Generally, in a semiconductor memory device such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an internal voltage generating circuit may be mounted. More efficient power consumption management and more stable circuit operation of the semiconductor memory device can be obtained by using an internal voltage generated by the internal voltage generating circuit. Such an internal voltage includes a core voltage, a precharge voltage and a cell plate bias voltage that are generated by down-converting an external power supply voltage, a pumping voltage and a substrate bias voltage that are generated by pumping the external power supply voltage.
Meanwhile, as semiconductor memory devices have become more highly integrated, design-criteria for making memory devices with dimensions below sub-micron level are applied to the semiconductor memory device and an operational frequency of the semiconductor memory device is also increased. For these extremely minute elements to perform operations at a high frequency, the external power supply voltage is decreased. Therefore, an importance of an internal voltage generated by using such a lowered external power supply voltage is being stressed more.
FIG. 1 is a circuit diagram illustrating a core voltage generating circuit for generating a core voltage VCORE as an internal voltage of a conventional internal voltage generating circuit.
Referring to FIG. 1, the core voltage generating circuit includes a voltage comparing unit 110, an activating unit 130, a driving unit 150 and a voltage dividing unit 170.
The voltage comparing unit 110 compares a reference voltage VREFC with a feedback voltage VFED and activates the driving unit 150 in response to a result of the comparison. Here, the reference voltage VREFC has a voltage value that corresponds or is at least substantially equal to a target voltage level of the core voltage VCORE (hereafter, referred to as a target voltage level).
The activating unit 130 enables the voltage comparing unit 110 in response to an enabling signal EN. That is, the comparing unit 110 performs the operation of comparing the reference voltage VREFC with the feedback voltage VFED in response to the enabling signal EN.
The driving unit 150 drives a terminal outputting the core voltage VCORE with an external power supply voltage VDD in response to an output signal of the voltage comparing unit 110. Although it will be explained later in the following operation explanations, the core voltage VCORE is increased to the target voltage level which corresponds or is at least substantially equal to the reference voltage VREFC by the driving unit 150.
The voltage dividing unit 170 generates the feedback voltage VFED by dividing the core voltage VCORE.
An operation of the core voltage generating circuit is briefly described as follows.
Firstly, a first N-channel Metal Oxide Semiconductor (NMOS) transistor NM1 of the activating unit 130 is turned-on in response to the enabling signal EN of a logic high. Since the core voltage VCORE initially has a lower voltage level than the target voltage level (that is, VREFC), the feedback voltage VFED has a lower voltage level than the reference voltage VREFC initially. The voltage comparing unit 110 initially outputs a signal of a logic low (that is, a low voltage level signal) with the reference voltage VREFC and the feedback voltage VFED lower than the reference voltage VREFC. In response to the low signal output of the voltage comparing unit 110, a first P-channel Metal Oxide Semiconductor (PMOS) transistor PM1 of the driving unit 150 is turned-on. Therefore, a driving current which corresponds to the external power supply voltage VDD is introduced to the terminal outputting the core voltage VCORE, and as a result, the core voltage VCORE gradually increases.
The above described operation is repeated continuously while the core voltage VCORE is increased to the target voltage level.
Meanwhile, if the core voltage VCORE becomes higher than the target voltage level, the feedback voltage VFED has a voltage level higher than the reference voltage VREFC. The voltage comparing unit 110 outputs a signal of a logic high with the reference voltage VREFC and the feedback voltage VFED higher than the reference voltage VREFC. Thereafter, the first PMOS transistor PM1 of the driving unit 150 is turned-off in response to the output signal of a logic high (that is, a high signal) of the voltage comparing unit 110. Accordingly, a driving current from the external power supply voltage VDD is no longer provided to the terminal of the core voltage VCORE. As a result, the increase in the core voltage VCORE is stopped.
In other words, the core voltage generating circuit in FIG. 1 maintains the core voltage VCORE at the target voltage level (that is, at VREFC) by repeating the above-mentioned steps of operations. The core voltage VCORE generated in this manner is applied to an internal circuit (not shown in the drawing) of a semiconductor memory device.
Meanwhile, in supplying electric power to circuits, leakage current often occur in these circuits. For example, leakage current often occurs in core voltage generating circuits such as the core voltage generating circuit in FIG. 1. Ideally, in case that the enabling signal EN becomes a logic low so that the voltage comparing unit 110 is disabled or in case that the core voltage VCORE is increased to the target voltage level so that the first PMOS transistor PM1 of the driving unit 150 is turned-off, current should not flown in the first PMOS transistor PM1. However, in reality, leakage current often occurs in the first PMOS transistor PM1. Leakage current also occurs in the voltage dividing unit 170 and the internal circuit, to which the core voltage VCORE is applied.
FIG. 2 is a diagram showing leakage current that accompanies a core voltage generating circuit.
In FIG. 2, there illustrated a leakage current source 212 and a leakage current sinking source 214, that are components of a core voltage generating circuit 210, and a leakage current sinking logic 230 where sinking leakage current occurs in logics of an internal circuit that the core voltage VCORE is provided.
The leakage current source 212 sources leakage current to the terminal outputting the core voltage VCORE and, for example, corresponds to the driving unit 150 in FIG. 1. The leakage current sinking source 214 sinks leakage current from the terminal outputting the core voltage VCORE and corresponds to the voltage dividing unit 170 in FIG. 1. Leakage current sunken by the leakage current sinking logic 230 sinks leakage current from the terminal outputting the core voltage VCORE and corresponds to the internal circuit that the core voltage VCORE is provided. In other words, in general, the leakage current introduced from the leakage current source 212 is discharged through the leakage current sinking source 214 and through the leakage current sinking logic 230.
FIG. 3 is a diagram for explaining the introduced current and the discharged current in connection with FIG. 2.
Referring to FIGS. 1-3, initially, during a period when the core voltage VCORE is gradually increased toward the target voltage level, leakage current discharged to a ground voltage terminal, i.e., the leakage current discharged through the leakage current sinking source 214 and through the leakage current sinking logic 230, is increased in response to increase in the external power supply voltage VDD. Thereafter, if the driving unit 150 is turned off in response to the core voltage VCORE reaching the target voltage level, leakage current discharged to the ground voltage terminal becomes a relatively constant value.
Meanwhile, initially, during the period when the core voltage VCORE is being gradually increased toward the target voltage level, all of the current introduced from the external power supply voltage terminal, i.e., the current sourced through the first PMOS transistor PM1 of the driving unit 150, is used for increasing the core voltage VCORE. With respect to leakage current, since current from the external power supply voltage terminal is intended, almost no current introduced from the power supply voltage terminal to the terminal outputting the core voltage VCORE is considered to be leakage current. Thereafter, if the core voltage VCORE is increased to the target voltage, source leakage current flows through the first PMOS transistor PM1 even if the first PMOS transistor PM1 of the driving unit 150 is turned-off. At this time, the source leakage current becomes more intensive as a voltage level of the external power supply voltage VDD is increased.
In other words, as a voltage level of the external power supply voltage VDD is increased, the leakage current introduced to the terminal of the core voltage VCORE from the terminal of the power supply voltage VDD becomes larger than sinking leakage current discharged to ground voltage terminal from the terminal of the core voltage VCORE.
FIG. 4 is a diagram showing a relation between the leakage current and the core voltage VCORE shown in FIG. 3.
As shown, the core voltage VCORE is maintained at the target voltage level to some degree even if the external power supply voltage VDD is increased. However, as above-described in relation to FIG. 3, as the external power supply voltage VDD is gradually increased, leakage current introduced to the terminal of the core voltage VCORE from the terminal of the power supply voltage VDD becomes larger than leakage current discharged to the terminal of the ground voltage VSS from the terminal of the core voltage VCORE. As a result, because of the surplus leakage current introduced to the terminal of the core voltage VCORE that is not sunken as a sinking leakage current, a voltage level of the core voltage VCORE becomes higher than the target voltage level.
Such an operation where leakage current makes the core voltage VCORE to become higher than a target voltage value is not desirable in an internal voltage generating circuit, where maintenance of the internal voltage generated at predetermined target voltage level is desirable. Also, the increased core voltage VCORE due to the leakage current applies unnecessary stress to an internal circuit that uses the core voltage VCORE. In such a case, the lifetime of the internal circuit may be shortened.